module counter(clk_out1,out[7:0]);
input clk_out1;
output [7:0] out;
reg [7:0] out;

always @(posedge clk_out1)
begin
out[3:0]<=out[3:0]+1;
	if(out[3:0]==9)
		begin	
			out[7:4]<=out[7:4]+1;
			out[3:0]<=0;
		if(out[7:4]==5)	
		out[7:4]<=4'd0;
		end
	
		
end

endmodule